The present invention relates to a semiconductor memory device and in particular to a semiconductor memory device, in which signal amplitude in data lines is small and data in a memory cell can be read out with a high speed.
A semiconductor memory device capable of reading out data stored in a memory cell with a high speed, which is known in the prior art, is described in 1992 IEEE International Solid State Circuit Conference. Digest of Technical Papers, pp. 208-209.
In order to shorten address access time for reading out data from a semiconductor memory device having two lines, i.e. a data line pair, generally it is useful to decrease signal amplitude in the data lines. Denoting the signal amplitude in the data line pair by .DELTA.V, parasitic capacitance of the data lines by C and current flowing through transistors driving the data lines by I, time t necessary for varying potential of the data lines is given by a following equation; EQU t=C.DELTA.V/I.
Consequently the time t is decreased by decreasing the signal amplitude .DELTA.V and thus a high speed operation is made possible. By the prior art techniques, in order to decrease the signal amplitude in the data lines, a current-sense type sense amplifier was used. Current flowing through a memory cell was introduced into a sense amplifier which transformed into voltage.